1. Field of the Invention
The invention relates to semiconductor technology and more particularly to a metallization structure with improved reliability.
2. Description of the Related Art
As semiconductor device circuit density increases and device feature size decreases, increased numbers of patterned metal levels with decreased spacing between metal lines at each level for effectively interconnecting discrete devices on semiconductor chips are required. Layers of insulating material or film, typically referred to as inter-layer dielectric (ILD) layers, separate different levels of metal interconnections. A common insulating material used for ILD layers is silicon oxide having a dielectric constant (k) of about 4.0 to 4.5 relative to vacuum having a k value of 1.0. As the spacing between the metal lines decreases, however, the intra-level and inter-level capacitances therebetween increases, as capacitance is inversely proportional to the spacing. It is therefore desirable to minimize the dielectric constant k of the insulating material between the metal lines to reduce the RC time constant, and thus, the performance of the circuit, for example, frequency response or the like, is improved because the signal propagation time in the circuit is adversely affected by the RC delay time.
When an insulating material having a dielectric constant k less than 3, often referred to as a low k material, is utilized for ILD layers between the metal lines, the adhesion between the low k material and metal line, is weaker than that between silicon oxide and metal line. Further, the linear thermal expansion coefficient of a conventional encapsulant for a package is typically greater than 10 ppm/° C., and that of silicon, one of the popular semiconductor materials, is approximately 3 ppm/° C. Thus, high thermal expansion coefficient mismatching results in exertion of thermal stress between a chip and encapsulant in the package. When a low k material is used for the ILD layers in the chip, the ILD layers suffer from potential delamination resulting from the exertion of thermal stress during assembly.